The present invention relates to a semi-conductor IC (Integrated Circuit) device having a memory integrated therein, and more particularly to a technique having the effective application thereof to a semi-conductor IC device in which a memory having a plurality of data transmission lines such as data input/output lines (I/O lines) and a logic circuit are integrated on the same semiconductor chip.
In recent years, the progress of LSI""s (Large Scale Integrated circuits) to high integration has been made so that it is being possible to integrate a large-capacity memory and a large-scale logic circuit or operation circuit on a semiconductor chip of about 1 cm square. In such chips, a very high speed equal to or higher than 1 G byte/sec can be attained as the rate of data transfer between the memory and the logic circuit or operation circuit by making the number of I/O lines of the memory equal to or greater than several hundreds. Therefore, such chips are expected to, for example, the use thereof for image processing or the like in which high-speed data transfer for a memory is required.
A first prior art applicable to such a purpose of use includes, for example, DRAM (Dynamic Random Access Memory) macros disclosed by Toshio Sunaga, et al., xe2x80x9cDRAM Macros for ASIC Chipsxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. 30, No. 9, September 1995, pp. 1006-1014. This reference has disclosed an LSI chip which includes the combination of a logic and a DRAM macro of 288K-bit (32Kxc3x979 bits) capacity having 9 (nine) I/O lines fabricated by 0.8 xcexcm CMOS technique, and an LSI chip which includes the combination of a logic and a DRAM macro of 1.25M-bit (64Kxc3x9718 bits) capacity having 18 (eighteen) I/O lines fabricated by 0.5 xcexcm CMOS technique.
As a second relevant prior art, U.S. Pat. No. 5,371,896 (issued Dec. 6, 1994) has showed a system in which a parallel computing system having many processors and memories coupled to each other is integrated on the same semiconductor chip. In this second prior art, a plurality of memories and a plurality of processors are integrated on the same semiconductor chip, and the memories and the processors are coupled by a network including crossbar switches. The second prior art is characterized in that an SIMD (Single Instruction Multi Data Stream) operation and an MIMD (Multi Instruction Multi Data Stream) operation can be performed in a changing-over manner, as required. At the time of SIMD operation, one of the plurality of memories is used as an instruction memory and the remaining memories are used as data memories. An instruction from the instruction memory is given to the processors in common with each other. At the time of MIMD operation, a part of the memories used as the data memories at the time of SIMD operation are used as instruction memories so that instructions from the separate instruction memories are given to the individual processors. Data transfer paths between the individual memories and the processors can be changed over to each other in various ways by the crossbar network.
Though various other semiconductor IC devices having memories integrated therein are devised in addition to the above-mentioned ones, it is being possible to integrate a high-integration memory such as DRAM (Dynamic Random Access Memory) and a logic circuit on the same semiconductor chip, as in the above-mentioned first prior art and attention is given to this technique in the fields of image processing and so forth.
The present inventors have revealed that such a semiconductor IC device involves two subjects.
A first subject concerns a design system. The conventional high-integration memories as discrete memories, especially DRAM""s are standardized in specification and hence they have a relatively long widely-used service life as products if they are manufactured once. Therefore, no great importance is attached to a design system for making a prompt design. However, a semi-condutor IC device having a high-integration memory such as DRAM and a logic circuit integrated on the same semiconductor chip as in the first prior art is needed, in many cases, for each specially fixed specification adapted to a specified application thereof. In general, therefore, a semiconductor maker will start in fabrication in compliance with a required specification after the acceptance of a requirement from a requester such as a user. Accordingly, the ability of prompt design is needed. In other words, the shortening of a time until the chip completion -from the start of chip design (or time to customers) is required. In addition, a variety of different memory capacities or kinds of operation circuits are required in accordance with the purpose of use. In order to satisfy such requirements for the period and the variety, it is necessary to make a reform from the design system.
A second subject concerns a coupling circuit for coupling a high-integration memory such as DRAM and a logic circuit which are integrated on the same semiconductor chip. In the case where the high-integration memory such as DRAM and the logic circuit are integrated on the same semiconductor chip, the mere integration thereof is difficult to bring about a large merit as compared with a discrete chip. If the cost and the required performance are taken into consideration, it is desirable that a large-capacity memory and a large-scale logic circuit such as operation circuit are integrated on a semiconductor chip of about 1 cm square so that several-hundred or more coupling lines can be ensured between the memory and the logic circuit to attain a high data transfer rate which is equal to or higher than, for example, 1 G byte/sec. Namely, it is desired that a coupling circuit for coupling the memory and the logic circuit is a high-speed and high-integration coupling circuit with which a data transfer path between the memory and the logic circuit (or operation circuit) can be changed in various ways.
The first prior art can overcome the first subject to some degree since it is possible to make the memory capacity variable by increasing and decreasing the number of DRAM macros, as required. In the first prior art, however, the number of I/O lines changes in proportion to the number of DRAM macros. Therefore, the first prior art has a problem that it is not possible to set the number of I/O lines and the memory capacity freely. Also, all peripheral circuits necessary for read/write operation are provided in each of DRAM macros having a relatively small capacity. Therefore, the first prior art has another problem that the overhead of the circuits becomes large if a multiplicity of DRAM macros are arranged. In order to make these problems more clear, the investigation will now be made in conjunction with the case where an LSI for image processing is constructed. For simplicity, it is assumed that each DRAM macro has a storage capacity of 256K bits and 8 (eight) I/O lines and the total number of I/O lines required in the LSI is 512. Then, the required number of DRAM macros is 64. The total storage capacity of the memory in this case amounts to 16M bits.
In the case where two-dimensional data is to be processed in the field of image processing, for example, in the case where a blurred image is to be reconstructed or in the case where characters or specified patterns are to be recognized, a high-speed ability is required even when such a memory capacity as mentioned in the above is not needed. In this case, if only the speed is taken into consideration, a multiplicity of DRAM macros of the first prior art can be arranged so that they are operated in parallel. However, there results in that the storage capacity of the memory becomes too large, thereby increasing the chip size. On the other hand, in the cage where three-dimensional data is to be processed, it is necessary to process a large amount of data at a high speed. It is possible to cope with this case by operating a multiplicity of DRAM macros in parallel, as mentioned above. However, there may be the case where a still greater number of I/O lines or a still larger storage capacity are required in accordance with a difference in the purpose of use such as domestic or industrial use or in accordance with the kind of data.
It is apparent from the foregoing that even in the same filed of image processing, various data transfer rates or various memory storage capacities are required in accordance with the purpose of use of a chip or the kind of data. Therefore, the mere preparation of DRAM macros with a fixed capacity as in the first prior art brings about various problems.
On the other hand, the second prior art concerns a coupling circuit for coupling memories and processors. In this second prior art, data transfer paths between the individual memories and the processors can be changed over to each other in various ways by crossbar switches. According to the second prior art, however, since the crossbar switches are used, a subject based on the above-mentioned second subject is caused. Namely, the second prior art has a subject that as the number of coupling lines is increased, the number of switches becomes enormous with an increase in scale of hardware and also an increase in delay. In the case where the data transfer paths between plural memories and plural processors independent of each other are changed over, as in the second prior art, a system used in the conventional parallel computer can be realized on the same chip, as it is, since the number of memories and processors is generally small. However, in the case where the correspondence between a group of several-hundred or more I/O lines of a memory and a group of I/O lines of a logic circuit such as operation circuit is changed over, the requirements for the degree of integration and the operating speed are severe and it is therefore difficult to use the conventional system, as it is.
Accordingly, one object of the present invention is to provide means for making a prompt design of a semiconductor device conformable to a required memory capacity or the kind of a required operation circuit. Namely, the object of the present invention is to provide a system for designing LSI chips conformable to various purposes in a short period of time and to provide a group of products based on that design system.
Another object of the present invention is to realize a memory macro which has a storage capacity capable of being made freely variable in a range from a small capacity to a large capacity and has a reduced overhead.
A further object of the present invention is to realize a memory macro which is suitable for ASIC (Application Specific Integrated Circuit) design.
A furthermore object of the present invention is to provide means for realizing, as a coupling circuit between a memory and a logic circuit, a high-speed and high-integration coupling circuit with which a data transfer path between the memory and the logic circuit (or operation circuit) can be changed in various ways.
The above and other subjects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
The term of memory core or memory macro means a circuit block including a memory cell array inclusive of a multiplicity of memory cells for storing information therein and a peripheral circuit for performing the reading and writing of data for the memory cell array. Though both the term of memory core and the term of memory macro are used in the present specification, they mean the same.
According to one aspect of the present invention, layout patterns of memory cores (MR) and a coupling circuit (TG) module set in compliance with the pitch of data transmission lines or I/O lines (MIOi) of each memory core (MR) are produced beforehand and are stored in a data base (DB). A logic library (LL) for composing a logic circuit is also produced and is stored in the data base (DB). Data such as those layout patterns, the specifications, characteristics and so forth necessary for design is stored in the data base (DB). The coupling circuit (TG) module is composed of a switch group (SWG) and a buffer group (TGBUFi) the combination of which can form a coupling circuit (TG). The switch group (SWG) is constructed by a plurality of switch groups (SWG) so that the order of inputted data can be replaced therein. With the setting of such plural switch groups (SWG), the switching control of a reduced number of stages of switches (SW) to provide a desired transfer pattern conformable to a transfer pattern (or transfer path) becomes possible, thereby enabling the high-speed change-over of transfer patterns. Since the coupling circuit (TG) module is constructed in conformity with the pitch of data transmission lines (MIOi) of the memory core (MR), as mentioned above, the coupling circuit (TG) module can be coupled to the data transmission lines (MIOi) of the memory core (MR), as it is, without requiring a change in layout pattern.
As mentioned above, the layout patterns of the memory cores (MR), the coupling circuit (TG) modules and the logic library (LL) are registered in the data base (DB) beforehand. Also, the pitch of wirings of the memory core (MR) and the pitch of wirings of the coupling circuit (TG) module are made even (or conformed to each other). Therefore, it is possible to use the memory module (MR) and the coupling circuit (TG) module so that they are coupled, as they are. Accordingly, the design of an LSI chip after a specification to be attained (for example, a specification from a user) has been definitely shown can be completed in a short period of time. Namely, this can be achieved in such a manner that a memory core (MR) having a required storage capacity and a module for producing a transfer circuit (TG) conformable to the specification are taken out of the data base (DB) and they are combined. Regarding a logic portion, a desired logic circuit (LC) can be composed from the logic library (LL) by use of a CAD (Computer Aided Design) tool for logic composition. The wiring between the memory core (MR) and the logic circuit (LC) can be performed by use of an arrangement/wiring CAD tool. Accordingly, a chip having a memory and a logic circuit integrated thereon can be designed in a short period of time.
In the coupling circuit (TG), data transferred between the memory core (MR) and the logic circuit (LC) passes through only an activated switch group (SWG). Therefore, high-speed data transfer can be realized. Further, since the number of stages of switch groups (SWG) is increased and decreased in accordance with the number of transfer patterns, there is no useless occupation area in the case where the number of transfer patterns is small.
In order to construct memories having various storage capacities in a short period of time, a memory macro (MMACRO) is constructed by the combination of functional modules such as an amplifier (AMP), a bank (BANK) inclusive of a memory cell array and a power supply (PS). Namely, there is provided a construction in which a multiplicity of data transmission lines (GBL, /GBL) extending in a bit line direction are arranged in the bank (BANK) module inclusive of the memory cell array and the data transmission lines are connected by merely arranging the modules so that they are adjacent to each other. Further, a circuit capable of activating and inactivating the data transmission lines in units of one byte is provided in the amplifier (AMP) module.
In a memory (MMACRO) having a plurality of banks (BANK), there are provided a plurality of addresses (Ri, Ci) which designate each bank. Thereby, it becomes possible to input an activation command (CR, AC, Ri) for one bank and a read or write command (CC, RW, Ci) for another bank in the same cycle so that the reading or writing over different banks can be performed in consecutive cycles.